Baidu
ACG · Baige AI Team / 百舸
AI Infrastructure · Talent program
Worked on improving the performance of LLM inference systems.
Changxu Liu 刘昶旭
Fifth-year Ph.D. student · Fudan University
I am a fifth-year Ph.D. student at the School of Microelectronics, Fudan University, advised by Prof. Fan Yang. I expect to graduate in 2027. I received my B.E. from Wuhan University in 2022.
My goal is to build efficient and elegant LLM inference systems. My recent work focuses on improving inference performance through advances in frameworks and algorithms, making LLMs more efficient to deploy and serve. I also have hands-on experience optimizing GPU kernels.
My earlier research focused on computer architecture and chip design, including hardware–software co-design and accelerators for AI and privacy-preserving computing. This background gives me a cross-layer perspective on system optimization: it helps me understand how decisions at the framework level affect memory access, the balance between computation and communication, and contention for hardware resources.
I am also interested in AI agents, especially their use in chip design. I would like to explore how agents can help engineers work through complex design tasks and improve productivity.
I am seeking full-time industry roles in AI infrastructure and LLM inference systems, starting in fall 2027. I would love to connect with teams turning research ideas into efficient, reliable systems for real-world use.
News
- Our work at Baidu on tree-structured speculative decoding for DeepSeek-V4 is now available as an arXiv technical report. Read more
- SparseBits was accepted for publication in IEEE TCAD. Read more
- SATLLM was accepted for publication in ACM TODAES. Read more
- Joined the Baige AI Team at Baidu ACG to work on LLM inference systems.
- HierPAS was accepted to DAC 2026. Read more
- Joined ByteDance's AI chip team to work on in-house computer architecture research.
- Received the National Scholarship for Doctoral Students (博士生国家奖学金).
- A Fault-Aware Architecture for Reliable Sparse Matrix Multiplication was accepted for publication in IEEE TCAD. Read more
- Joined Tencent's AI Data Platform team in TEG through the Talent program (青云计划).
Internship Experience
ByteDance
Data-PH · AI Chip Team
Formally modeled and verified memory consistency for in-house chips and explored in-house GPGPU architectures.
Tencent
TEG · AI Data Platform
Talent program / 青云计划
Researched custom AI-chip architectures and optimized model inference.
Research & Publications
- AI infrastructure and model inference. Improving LLM inference performance through research on frameworks and algorithms.
- Hardware–software co-design. Computer architecture and accelerator design for AI and privacy-preserving computing.
2026
SATLLM: A Sparsity-aware Accelerator for Ternary-Weight Large Language Models
Joint algorithm and architecture design to exploit sparsity in ternary-weight LLMs.
Adapting Tree-Structured Speculative Decoding to DeepSeek-V4 for Efficient Inference
Tree-structured speculative decoding for efficient inference with DeepSeek-V4.
HierPAS: Accelerating Video Generation Models with Hierarchical Precision and Adaptive Sparsity
Adaptive sparsity and mixed precision to accelerate inference in video generation models.
A Fault-Aware Architecture for Reliable Sparse Matrix Multiplication
Fault-aware data scheduling and accelerator design for reliable sparse matrix multiplication.
SparseBits: Sparse Ternary LLM Acceleration with L1-regularized Cluster-aware Sparsification
Cluster-aware sparsification, sparse scheduling, and accelerator co-design for ternary-weight LLMs.
2025
AcclMT: A Highly Resource-Efficient and Flexible Poseidon Hash-Based Merkle Tree Architecture
A flexible hardware architecture for efficient Poseidon hashing and Merkle-tree construction.
GEMMHeal: An Efficient Self-repairing Architecture for Matrix Multiplication
A self-repairing matrix-multiplication architecture for reliable AI computation.
2024
Myosotis: An Efficiently Pipelined and Parameterized Multi-Scalar Multiplication Architecture via Data Sharing
Data sharing and pipelining for flexible, efficient multi-scalar multiplication.
ReZK: A Highly Reconfigurable Accelerator for Zero-Knowledge Proof
A reconfigurable hardware accelerator for zero-knowledge proof workloads.
PriorMSM: An Efficient Acceleration Architecture for Multi-Scalar Multiplication
Parallel bucket aggregation and priority-based scheduling for multi-scalar multiplication.
Gypsophila: A Scalable and Bandwidth-Optimized Multi-Scalar Multiplication Architecture
A scalable multi-scalar multiplication architecture designed to reduce memory-bandwidth demands.
HMNTT: A Highly Efficient MDC-NTT Architecture for Privacy-preserving Applications
An efficient number-theoretic transform architecture for privacy-preserving computation.
A Fully Pipelined Reconfigurable Montgomery Modular Multiplier Supporting Variable Bit-Widths
A pipelined, reconfigurable modular multiplier supporting variable operand widths.
* Equal contribution.